Logic SER In High-Performance Microprocessors – Myth and Reality

CMOS circuitries are susceptible to soft errors induced by alpha particles or neutron bombardment. The bombardment creates excess carriers in the drain regions of the MOS devices and changes, or temporarily distorts, the voltage values of the charge storage nodes, creating errors in memory arrays or logic elements [1,2,3]. Depending on its criticality, the resulting soft error may or may not lead to a user visible failure at the system level (system crash, etc.). A derating factor is used to account for this fact. In derating, the raw FIT rate of a device, obtained via simulation or measurement, is derated by its utility factor. While the derating process for memory SER is relatively well studied and understood, the derating process for logic SER (LSER) is much less so because error propagation behaviors in logic elements are much more complicated.